Example embodiments of the present inventive concepts relate to methods of fabricating semiconductor devices, and in particular, to hardmask structures, and methods of forming patterns using the same.
A variety of technologies have been developed to increase the integration density of a semiconductor device by forming extremely fine patterns on the semiconductor substrate. For example, multi-layer lithography technology, double or quadruple patterning technology, and V-NAND technology have been used to increase the integration density of semiconductor devices. To realize such technologies, a plurality of layers may be stacked on a substrate. However, depending on the structure and shape of an underlying pattern, the stack of layers may have a portion whose thickness or height is different from other portions. This height difference may lead to technical issues, such as deterioration in uniformity in critical dimensions (CD), and/or to difficulties in forming patterns in subsequent processes.